Cache memories are widely used in contemporary computer systems to improve, on a statistical basis, the effective access time between a precessor and main memory. The typeical cached system uses a modest amount of fast-access static RAM as a buffer between the processor and a much larger array of slower, denser dynamic RAM devices. The benefit of a large cache is average access times approaching that of the fast static memory. Its costs include the static RAM whose contents are redundant with the selected portions of dynamic memory, additional tag memory used in recording addresses of cache contents, and comparators and other associated logic.
Modern static column dynamic RAM (SCRAM) chips combine a fast static row buffer with a much larger dynamic charge array. An entire row of the two-dimensional array, dictaterd by high-order address bits, is loaded into the row buffer on the row address strobe (RAS) signal. Subsequent accesses to memory elements within that row may be made at static RAM speeds since they deal only with the static buffer. The effect is to achieve very fast access times to consecutive locations within the same row, while exploiting DRAM densities for the bulk of the memory.
The static row buffer is reminiscent of a cache, and its use as such has been proposed by Goodman and Chiang, "The Use of Static Column RAM as a Memory Hierarchy", The 11th Annual Symposium on Computer Architecture, IEEE Computer Society Press, 1984, pp. 167-174. In the Goodman-Chiang system, each of several banks of static column RAM has an associated location in a tag memory. The tag memory records the currently buffered row address for each memory bank, and the system avoids the RAS time overhead when a new memory transaction references the same row as the last transaction to that bank. The high-order address bits of an incoming transaction dictate the affected memory bank and consequently the tag memory location to be accessed. The remaining address bits comprise a row address and a column address, the latter being consigned to the low order. If the fetched tag memory contents match the incoming row address bits, a static column "hit" takes place: the column address bits are used to address the requested location in the current row buffer of the selected bank. Otherwise, a slower "miss" ensues: a RAS cycle is used to store the current row back into the charge array and to fetch the row indicated by the new row address.
Since only the column address is needed to initiate a static-column access, read transactions may overlap tag memory access with interrogation of the row buffer on the optimistic expectation of a hit. Thus in this most common case, the major time cost of a read hit is just the static column access time which is similar to that of a conventional cache consisting of separate static RAM.